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Connectivity line devices: reset and clock control (RCC)
RM0008
Bits 3:0 PREDIV1[3:0] : PREDIV1 division factor
Set and cleared by software to select PREDIV1 division factor. These bits can be written only
when PLL is disabled.
Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the
RCC_CFGR register changes Bit(0) accordingly.
0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16
7.3.13
Table 16.
RCC register map
The following table gives the RCC register map and the reset values.
RCC register map and reset values
Offset
Register
0x000
RCC_CR
Reser
ved
Reserved
HSICAL[7:0]
HSITRIM[4:0]
Reset value
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
1
0
0
0
0
1
1
0x004
RCC_CFGR
Reserved
MCO [3:0]
PLLMUL [3:0]
ADC
PRE
[1:0]
PPRE2
[2:0]
PPRE1
[2:0]
HPRE[3:0]
SWS
[1:0]
SW
[1:0]
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x008
RCC_CIR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00C
RCC_APB2RSTR
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0x010
RCC_APB1RSTR Reser
ved
Reserved
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
136/995
Doc ID 13902 Rev 9
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